1. Field of the Invention
The present invention relates to control signals in computer systems, and more particularly to an apparatus for modifying a locking signal in a computer system to lengthen the period of the signal and to allow interruption of the lock signal on consecutive locked cycles for arbitration purposes.
2. Description of the Related Art
Computer systems continue to increase in size and complexity. Most modern computer systems include one or more microprocessors in addition to intelligent bus masters and other devices which are capable of taking control of the bus to perform bus cycles. The microprocessor and the various bus masters and devices vie for control of the bus to access necessary code and data and perform useful work. In modern computer systems, it is necessary to ensure that certain cycles being executed by the processor are protected from being split up by another requesting device. An example of cycles that need this type of protection are read-modify-write cycles. In a read-modify-write cycle, the processor reads a memory location to determine its contents and then modifies the location by writing back a new data value. Read-modify-write cycles are commonly used in computer systems to implement memory-based semaphores. In executing read-modify-write cycles, it is important that the bus not be relinquished by the processor between the matching read and write cycles to ensure that the variable being modified is not accessed between the read and the write. With regard to read-modify-write cycles, it is noted that locked cycles may occur as a read-modify-write cycle, a read-read-modify-write-write cycle, a read-read-modify-write cycle, or a read-read cycle. Other cycles which require protection to prevent the processor from relinquishing the bus are any operand transfers which require more than one bus cycle. Examples of such transfers are 64 bit floating read and write cycles, 64 bit descriptor reads, and cache line fills.
In order to provide adequate protection and prevent the processor from relinquishing the bus during a read-modify-write cycle or one of the other cycles requiring protection, locked cycles were developed. Most modern microprocessors include one or more LOCK signal outputs which indicate that the processor is performing a read-modify-write cycle or other cycle requiring protection and that the bus must not be relinquished during this time. For example, the Intel Corporation (Intel) i486 microprocessor includes a bus LOCK output referred to as CPULOCK*. The asserted CPULOCK* signal indicates that the i486 processor is running a read-modify-write cycle. When the CPULOCK* signal is asserted, the current bus cycle is locked, and the i486 microprocessor is allowed exclusive access to the system bus. The i486 processor does not acknowledge a bus hold request when the CPULOCK* signal is asserted. The CPULOCK* signal goes active in the first clock cycle of the first LOCKed bus cycle and goes inactive after the ready signal is returned indicating the completion of the last LOCKed bus cycle. The i486 processor also generates a signal referred to as PLOCK*, which is asserted to guarantee exclusive access to the bus during reads and writes of operands greater than 32 bits.
Background on the Extended Industry Standard Architecture (EISA) is deemed appropriate. EISA is a superset of the Industry Standard Architecture (ISA), a bus architecture introduced in the International Business Machines Corporation (IBM) PC/AT personal computer. EISA based computer systems utilize a standard chip set which includes among others an EISA bus controller (EBC). The EBC interfaces between the memory or host bus and the expansion bus or EISA bus and includes clock generation logic, bus interface logic, DMA interface logic, bus master interface logic, and buffer control logic, among others. Preferably the EBC is the 82358 from Intel, or its equivalent.
Most modern computer systems also generally include cache memory systems. Cache memory is a small amount of very fast, and expensive, zero wait state memory used to store frequently accessed code and data. One example of a cache controller used in cache memory systems is the C5 or 82495 cache controller produced by Intel Corporation (Intel). The C5 cache controller is designed to operate with the i486 processor. The C5 cache controller receives the locking signals produced by the microprocessor, for example, the CPULOCK* and the PLOCK* signals from the i486 processor, and generates two similar signals referred to as KLOCK* and CPLOCK* respectively. The CPLOCK* signal tracks the PLOCK* signal generated by the i486 processor and is only generated for write cycles. When consecutive write cycles are PLOCKed together, snooping is disabled between these cycles. The CPLOCK* signal is only generated during write cycles because the C5 cache controller operates all read cycles as uninterruptible burst transfers, and thus locking is unnecessary for read cycles. The CPLOCK* signal is active for the first write of a CPLOCKed operation and goes away with the assertion of the next address or ready signal of that write. The CPLOCK* signal is not asserted for the second write operation. The KLOCK* signal is asserted by the C5 cache controller to the memory controller to indicate a request to execute read-modify-write cycles. The KLOCK* signal is a one-clock flow-through version of the CPULOCK* signal. The C5 cache controller activates the KLOCK* signal with the cache address strobe signal CADS* on the first cycle of a LOCKed operation, and the KLOCK* signal remains active until the CADS* signal is asserted on the last cycle of the LOCKed operation, i.e., the final write of a read-modify-write sequence. Thus the KLOCK* and CPLOCK* signals output from the C5 cache controller are not valid during the entire last LOCKed cycle. However, the EISA bus controller (EBC) requires that the LOCK* signal it receives at its input be valid throughout the entire LOCKed cycle. Therefore, problems arise when the C5 cache controller is incorporated into an EISA based computer system utilizing the EBC.
Another problem that arises with the C5 cache controller locking signals generated by the C5 cache controller is that, when pipelining is implemented by the microprocessor, it is possible for the KLOCK* signal on the host bus to remain active from one locked cycle to the next, thus preventing other bus masters or devices from arbitrating for control of the bus during this time. During back-to-back LOCKed cycles, the KLOCK* signal output from the C5 cache controller will generally remain asserted, thus blocking other devices from obtaining the bus. Therefore, when pipelining is implemented, situations arise wherein the deactivation of the KLOCK* signal occurs on the same clock edge as its new activation, and in this instance the KLOCK* signal does not go inactive between back-to-back LOCKed sequences. One method that could be used to allow arbitration windows between back-to-back LOCKed cycles is to detect a LOCKed write followed by a LOCKed read. A LOCKed read following a LOCKed write signifies that the prior LOCKed write was the last write of a read-modify-write cycle and that the LOCKed read is the first read of a subsequent read-modify-write cycle. However, a problem with this method occurs because detecting a LOCKed write followed by a LOCKed read does not provide a sufficient amount of time in order to halt the execution of the LOCKed read and allow arbitration for the bus. If the method of detecting a LOCKed read following a LOCKed write is used, the read cycle may already begin before there is time to halt the cycle and allow arbitration. Therefore a method and apparatus which allows arbitration between back-to-back LOCKed sequences is desired.